1. Field of the Invention
The invention relates to a periodic voltage pulse generator for driving the electrodes or groups of electrodes of a plasma display panel, these being used both for the address and the sustain phases.
2. Description of the Related Art
An AC plasma display panel (or PDP) with memory effect generally comprises two parallel plates leaving between them a space containing a discharge gas; these plates are provided on their internal faces with arrays of electrodes covered with a dielectric layer:    generally two arrays of intersecting electrodes are used for the address phase, at the intersections of which, in the space between the plates, light discharge regions are defined;    at least two arrays of electrodes being used for sustaining.
In the case of coplanar panels, the two sustain arrays are formed from electrodes placed on the same plate and the general directions of which are parallel; each electrode of a sustain array forms with an electrode of the other sustain array a pair of electrodes defining between them a succession of light discharge regions, generally distributed along a line of pixels of the panel.
In the case of matrix panels, the two sustain arrays are no longer coplanar and are located on different plates.
The light discharge regions form, on the panel, a two-dimensional matrix of points capable of emitting light in order to display the image to be displayed.
In general, at least one of these arrays of electrodes is used both for addressing and for sustaining; the invention relates to a generator for an array of electrodes of this type.
The adjacent discharge regions, at least those emitting different colours, are generally bounded by barrier ribs; these barrier ribs generally serve as spacers between the plates.
The walls of the light discharge regions are in general partially coated with phosphors sensitive to the ultra-violet radiation of the light discharges; adjacent discharge regions are provided with phosphors emitting different primary colours so that the combination of three adjacent regions forms a picture element or pixel.
To display an image, the plasma panel in operation carries out a succession of scans, or sub-scans, of the matrix of dots or discharge regions to be activated or not; each scan or sub-scan generally comprises the following steps:    firstly, a selective addressing step whose purpose is to deposit electrical charges on that portion of the dielectric layer of the discharge regions which is to be activated, by applying at least one voltage pulse between the address electrodes intersecting in these regions; and then    a non-selective sustain step during which a succession of voltage pulses is applied between the electrodes of one and the same sustain pair so as to cause a succession of light discharges only in the discharge regions located between these electrodes that have been addressed beforehand.
Some of the scans or sub-scans of the panel may furthermore include other phases, such as erase or priming phases, which involve the application of specific voltage pulses; these pulses generally have specific characteristics, not only as regards the hold voltage (high or low hold) but also as regards the voltage rise and/or fall ramps.
The application of voltage pulses between the electrodes of various arrays of the panel, such as those that have just been described, induces cycles charging and discharging the electrical capacitor that these electrodes form between them; as the sustain steps represent by far the highest number of charging and discharging cycles, it is general practice to use, to generate the sustain pulses, generators based on resonant circuits, allowing the capacitive energy between the electrodes to be recovered and re-injected.
FIG. 1 shows diagrammatically a first example of a sustain pulse generator 2′ supplying an electrode Yn of an array Y of a plasma panel 1, the said electrode facing an adjacent electrode Y′n belonging to another sustain array of this panel; this generator is an energy recovery generator and is described in the document U.S. Pat. No. 4,707,692 (Higgins); to obtain the sustain voltage pulses, this electrode Yn is alternately switched to a positive DC sustain voltage VS and to a DC reference voltage Vref via voltage switches 22′ and 23′ connected in series, respectively; the DC sustain voltage VS is greater than the reference voltage Vref; since these switches are generally MOSFET-type transistors, they each have, in parallel at their terminals, an intrinsic diode 24′ and 25′ respectively, oriented so as to be conducting from the common point of these switches to the sustain potential VS and from the reference potential Vref to the common point of these switches, respectively; a resonant inductor 20′, connected between the common point of these switches and the electrode Yn to be supplied, and a storage capacitor 21′, connected between the common point of these switches and the reference potential Vref (or the sustain potential VS), allow the capacitive energy to be recovered and re-injected between each alternation; finally, between the electrode Yn to be supplied and the sustain voltage VS on the one hand, and between the electrode Yn to be supplied and the reference voltage Vref on the other hand, the circuit has voltage clamping means connected in series; these means may be simple diodes 26′, 27′ oriented so as to be conducting in the same direction as the diodes 24′, 25′ described above of the voltage switches 22′, 23′, that is to say respectively from the common point of these clamping means to the sustain potential VS and from the reference potential Vref to the common point of these clamping means; according to a variant shown by the dotted lines in FIG. 1, these clamping means furthermore include voltage switches 28′, 29′ in parallel with each clamping diode 26′, 27′; these switches 28′, 29′ make it possible in particular to compensate for the energy recovery and re-injection losses; in practice, they are generally MOSFET transistors and the clamping diodes 26′, 27′ then correspond to the intrinsic diodes of these transistors; the resonant inductor 20′ and the storage capacitor 21′ are designed to obtain the resonant mode described in the document U.S. Pat. No. 4,707,692 in conjunction with the capacitor between the electrodes of the panel.
FIG. 2 shows diagrammatically a second example of a sustain pulse generator 2 supplying an electrode Yn of the same plasma panel 1; this generator is an energy recovery generator and is described in the document U.S. Pat. No. 4,866,349 (Weber); to obtain the sustain voltage pulses, this electrode Yn is alternately switched to a positive DC sustain voltage VS and to a DC reference voltage Vref via voltage switches 22 and 23 connected in series, respectively; the DC sustain voltage VS is, as previously, greater than the reference voltage Vref; since these switches are generally MOSFET transistors, they each present, in parallel at their terminals, an intrinsic diode, 24 and 25 respectively, oriented so as to be conducting from the common point of these switches to the sustain potential VS and from the reference potential Vref to the common point of these switches, respectively; to recover and re-inject the capacitive energy, the generator 2 includes a resonant inductor 20, a transferred-energy switching module 30 and a storage capacitor 21 which are connected in series between, on the one hand, the electrode Yn to be supplied, which corresponds to the common point of the switches 22, 23, and, on the other hand, the reference potential Vref (or the sustain potential VS); the transferred-energy switching module 30 comprises here two transfer elements in parallel, each element itself comprising a switch and a diode in series, the diode of the first element being oriented so as to be conducting in the opposite direction to the diode of the second element, and the intrinsic diode of the switch of each element being oriented in the opposite direction to the diode in series with this element; as illustrated in FIG. 7 of the abovementioned document U.S. Pat. No. 4,866,349, the sustain generator 2 also includes means for clipping the voltage at the common point of the inductor 20 and of the transferred energy switching module 30 by means of diodes 26, 27; the resonant inductor 20 and the storage capacitor 21 are designed to obtain the resonant mode described in document U.S. Pat. No. 4,866,349 in conjunction with the capacitor between the electrodes of the panel.
FIG. 3 shows three voltage pulse timing diagrams, namely that applied to the electrodes Yn of the sustain and address array Y, that applied to the electrodes Y′n of the sustain array Y′ and that applied to the electrodes Xp of only an address array X, which intersect the electrodes Yn of the sustain and address array Y.
These timing diagrams represent a succession of successive phases belonging to the same scan or sub-scan cycle of the plasma panel, namely the priming phase PP, the erase phase PE, the address phase PA and the sustain phase PS.
The generators 2 and 2′ that have just been described are used, in the case of the sustain phase PS to apply voltage pulses VS to the electrodes or the groups of electrodes YN that serve both for the sustain and for other drive phases of the panel.
The electrodes Y′n of the array Y′ that are used only for the sustaining are generally connected together and then form what is called the “common” array; they are generally supplied by an energy recovery generator of the same type as that which supplies the electrodes Yn of the array Y, such as that described in FIG. 1 or 2; the entire supply for the electrodes during the sustain phases will be described later with reference to FIG. 7 or FIG. 8; according to the timing diagrams shown in FIG. 3, this generator delivers voltage pulses V′S in phase opposition to the sustain voltage pulses VS that supply the electrodes Yn used both for sustain phase and the address phase.
As regards the driving of the electrodes Yn of the sustain and address array Y, the method of driving the panel, shown in FIG. 3, comprises the application of voltage pulses that have different values relative to the reference voltage Vref:    values always greater than the reference voltage Vref, namely as regards the priming voltage VP, as regards the “high” address voltage VAH and as regards the sustain voltage VS;    values close to the reference voltage Vref, while still being here greater than or equal to it, namely as regards the erase voltage VE and as regards the “low” address voltage VAL.
The “high” address voltage VAH corresponds to a bias voltage applied simultaneously to all the electrodes Yn of the sustain and address array Y (except for one electrode) throughout the address phase PA; the “low” address voltage VAL corresponds to a short address pulse applied selectively to an electrode Yn and which, in possible combination with a voltage pulse VD applied to the electrodes Xp of the array X of columns, allows selective deposition of the charges only in those discharge regions to be activated that are supplied by this electrode Yn.
FIG. 4 shows diagrammatically a supply device 10 for applying the drive method shown by the timing diagram VY shown in FIG. 3 to an electrode Yn of a sustain and address array Y; this device comprises several generators connected in parallel between this electrode Yn to be supplied and the reference potential Vref:    an energy-recovery sustain pulse generator 2 of the Weber type described above with reference to FIG. 2;    at least one signal generator 3 having a potential above the reference potential Vref, in this case a bias generator suitable for applying the potential VAH>Vref during the address phase;    at least one signal generator 4 having a potential close to the reference potential Vref, in this case an address pulse generator designed to apply the address potential VAL.
To be able to apply the drive method shown by the timing diagram VY of FIG. 3 to each of the electrodes Yn of the sustain and address array Y, with reference to FIGS. 5 and 6, each electrode Yn of this array is connected to the output of the three generators 2, 3, 4 described above via a line driver 5; each line driver conventionally comprises:    two driver switches 51, 52 in series, the common point of these switches being connected to the electrode Yn to be supplied, the outermost terminals of this series of switches forming an upper switched terminal and a lower switched terminal;    two driver diodes 53, 54 in series, the common point of these diodes also being connected to the electrode Yn to be supplied, the outermost terminals of this series of diodes forming an upper power terminal and a lower power terminal.
With reference to FIG. 6, all the upper switched terminals of the various drivers 5′ are connected together and form a common upper switched terminal 552; all the lower switched terminals of the various drivers 5 are connected together and form a common lower switched terminal 562; all the upper power terminals of the various drivers 5 are connected together and form a common upper power terminal 551; all the lower power terminals of the various drivers 5 are connected together and form a common lower power terminal 561.
For each driver, each driver diode 53 called the “upper” driver diode is oriented so as to be conducting from the common point with the other diode of the series to the common upper power terminal 551, and each driver diode 54 called the “lower” driver diode is oriented so as to be conducting from the common lower power terminal 552 to this same common point.
During the sustain phases, all or practically all the electrodes must be connected simultaneously to the sustain generator 2 so that the electrical current flowing at the common terminals is very high; since the driver switches 51, 52, which are generally of the MOSFET type, would not withstand such currents, it is highly preferable to prevent these sustain currents from flowing via these switches; during the sustain phases where no switching is in general necessary, the electrodes Yn of the panel 1 are therefore supplied via the driver diodes 53, 54 designed to withstand the flow of high currents.
To be able to manage the supply for the electrodes differently, depending on whether or not the system is in the sustain phase, several solutions are conventionally used:    in the first solution shown in FIG. 5, each driver has only two input terminals, namely an “upper” input terminal 55 and a “lower” input terminal 56, since the common upper switched terminal 552 and the common upper power terminal 551 are coincident and the common lower switched terminal 562 and the common lower power terminal 561 are also coincident; this simplification of the drivers 5 involves the addition of a power switch 6 between the upper input terminal 55 and the lower input terminal 56, this switch being closed during the sustain phases of the panel so as to be able to supply the electrodes Yn of the panel 1 via the upper power diode 53 or via the lower power diode 54 depending on the off-cycles of the sustain pulses delivered by the generator 2, the driver switches 51, 52 then being open;    in the second solution, shown in FIG. 6, such a power switch is unnecessary since the supplies for the electrodes, on the one hand via the driver diodes 53, 54 and on the other hand via the driver switches 51, 52 are distinct and separate; the common upper power terminal 551 and the common lower power terminal 561 that are used only during the sustain phases are both connected to the same output terminal of the sustain generator 2; moreover, as previously, the upper switched terminal 552 is connected to the output of the signal generator 3 having a potential above the reference potential Vref and the lower switched terminal 562 is connected to the output of the signal generator 4 having a potential close to the reference potential Vref.
FIG. 7 shows diagrammatically the entire device for supplying the electrodes of the plasma panel 1, this comprising:    the device 10 for supplying the electrodes Yn of the sustain and address array Y described previously in FIG. 5;    a supply generator 11 for the electrodes Y′n of the sustain array Y′; and    a generator 12 for supplying the electrodes Xp of the address array X, this being capable of delivering voltage pulses VD (see FIG. 3); this generator, known per se, will not be described here in detail.
FIG. 8 shows an alternative embodiment of the device for supplying the electrodes shown in FIG. 7, the essential difference lying in the fact that the same means for recovering the capacitive energy of the generator 2′, of the type of those of the generator shown in FIG. 2, are used for supplying the electrodes of both sustain arrays Y and Y′.
In general, to prevent the electrodes Yn of the sustain and address array Y from being subjected to the pulses of the sustain generator from their supply device during the phases other than the sustain phase, especially the address phase, this sustain generator is, if necessary, stopped during these phases.
Some plasma panel drive methods include the application of voltage pulses having values below the reference voltage Vref; in FIG. 9 illustrating an example of such a method, the erase voltage VE applied during the erase phase PE and the low address voltage VAL applied during the address phase PA are below the reference voltage Vref (see the arrows directed upwards  in the figure); during application of such a voltage as VAL by means of a supply device 10 or 10′, as described above, and shown in FIGS. 5 and 6 respectively, there would then be a short-circuit via the intrinsic diode 25 at the terminals of the voltage switch 23 of the energy-recovery sustain pulse generator 2; in the case of the generator 10′ shown in FIG. 6, this short-circuit also passes via the lower diodes 52 of the drivers 5′; the generator 2″ in FIG. 8 has the same drawbacks.